New memory architecture targets AI inference bottlenecks

Lightbits Labs Ltd. today is introducing a new architecture aimed at addressing one of the most stubborn bottlenecks in large-scale artificial intelligence inference: the growing mismatch between the ...
Semiconductor Engineering

RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)

A Reasoning Processing Unit”. Abstract “Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they ...
Electronic Design

New Architecture Enhances Memory Test and Repair

Generic test and repair approaches to embedded memory have hit their limit. Smaller feature sizes, such as 130 nm and 90 nm, have made it possible to embed multiple megabits of memory into a single ...
VentureBeat

GAM takes aim at “context rot”: A dual-agent memory architecture that outperforms long-context LLMs

For all their superhuman power, today’s AI models suffer from a surprisingly human flaw: They forget. Give an AI assistant a sprawling conversation, a multi-step reasoning task or a project spanning ...
techtimes

AMD Patents New DDR5 Memory Architecture to Double Data Rates, Boost Performance

AMD submitted a patent to the World Intellectual Property Organization (WIPO) for a groundbreaking new memory architecture that can significantly enhance the performance of the DDR5 standard. The ...