EDN

Generate FPGA designs from M-code

DSP systems are best described by using a combination of both graphical-and language-based methods. The MathWorks, an industry leader in DSP modeling software, caters to this dichotomy by providing a ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
Electronic Design

PCs Bridge The Gap Between DSP And FPGA Designers

Typically, DSP designers are unfamiliar with FPGA design tools, and FPGA designers are unfamiliar with DSP algorithms. But when Sandia National Laboratories needed to replace an analog implementation ...
Design-Reuse

Altera Offers First C-code-based DSP Design Flow for FPGAs

San Jose, Calif., September 4, 2002 —Altera Corporation (NASDAQ: ALTR) today announced the availability of the FPGA industry's first C-code-based design flow for digital signal processing (DSP) ...
Electronic Design

FPGA Tool Beckons DSP Designers

Most analysts agree that this year, the growth rates of field-programmable gate arrays (FPGAs) will actually double that of application-specific integrated circuits (ASICs). Of course, FPGAs have been ...
Design-Reuse

Altera First to Benchmark Complex High-Performance Floating-Point Digital Signal Processing Designs on 28 nm FPGAs

Altera’s DSP Builder Advanced Blockset™ Design Flow Verified by BDTI, the Industry's Most Trusted Source of Independent DSP Technology Analysis San Jose, Calif., October 29, 2012— Altera ...