More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.

A new technical paper titled “Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?” was published by researchers at Universität Kaiserslautern-Landau and Infineon Technologies.

SAN JOSE, Calif. — Formal verification won't replace dynamic verification, but improved tools and methodologies will result in more widespread use of formal techniques, according to panelists at the ...

In recent years, formal verification has become the verification methodology of choice for many designers and verification engineers. It's now in the mainstream marketplace, as it's easy to use, ...

Automata learning and formal verification represent converging fields aimed at enhancing the reliability and safety of complex systems. Automata learning involves the algorithmic inference of system ...

PARTNER CONTENT Given the size and complexity of modern semiconductor designs, functional verification has become a dominant phase in the development cycle. Coverage lies at the very heart of this ...

Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging ...

Formal methods provide a rigorous mathematical foundation for the specification, development and verification of medical device software. This approach enhances both reliability and safety, which are ...

Formal verification is a process that mathematically proves the correctness of a system, ensuring it “behaves exactly as intended under all defined conditions.” the CertiK team notes in a blog post.

Recent work directed by professors Ronghui Gu and Jason Nieh introduced a new tool, Spoq, that significantly reduces the complex efforts people must use to verify real-world software and makes it ...

Figure 6 shows how formal power-grid verification fits into a power-grid-sign-off flow. As soon as a designer lays out the power-grid distribution and places the hard macros at the floorplan stage, ...