Business Wire

Imperas Delivers First RISC-V Simulator for New Vector and Bit Manipulation Specifications to Lead Customers

OXFORD, England--(BUSINESS WIRE)--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the delivery of its updated simulator for the RISC-V ...
EDN

AI is stress-testing processor architectures and RISC-V fits the moment

RISC-V’s expanding role in AI is not a rejection of incumbent architectures, which continue to deliver performance and compatibility across a wide range of systems. It reflects a shift in engineering ...
AppleInsider

New Geekbench update adds RISC-V and improves ARM Extension Support

Benchmarking tool Geekbench has been updated to version 6.4, seeing added support for RISC-V Vector Extensions and Arm Scalable Matrix Extensions. Geekbench is a highly-used benchmark tool, providing ...
Design-Reuse

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...
Business Wire

SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which ...