EDN

Getting in sync with UVM sequences

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Semiconductor Engineering

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2 ...
EDN

UVM Reactive agents verify with a handshake

UVM (Universal Verification Methodology) is widely used in creating object-oriented test environments. UVM provides two key benefits to verification engineers; one is reusability; the other is ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
EDN

Co-emulation for better IC testing

While IC design complexity increases, the amount of time allotted for designing ICs remains about the same. That compels engineers to accelerate all the processes involved. I’m a member of a team that ...
EDN

Synopsys Expands Verification IP Portfolio with Memory Models

“To deliver the DDR3/DDR4 memory technologies in our advanced 64-bit AMD Opteron™ A-Series server SoC, formerly code-named 'Seattle,' we were an early user of the Synopsys DDR verification IP as part ...
EDN

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a ...
EDN

Inside Portable Stimulus: UVM Integration

Integrating Portable Stimulus Standard (PSS) capabilities with the Universal Verification Methodology (UVM) is not the same as an integration between two languages. In our previous column, Aileen ...
EDN

Reuse existing verification assets with the Portable Test and Stimulus Standard

The productivity promise of portable stimulus has rapidly become well known in our industry. The high level of interest exhibited in the Accellera Portable Test and Stimulus Standard (PSS) makes sense ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

Indeed, designers have embraced SystemVerilog—it's by far the fastest growing design/verification language in the world today (Fig. 1). "The ability to do assertions is significantly improved in ...