Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.

MS in Electrical & Computer Engg. Seeking entry level positions in the digital hardware sector, i.e. FPGA emulation, VLSI/ASIC Design, Logic Design, Digital Systems & Embedded Systems.

SAN FRANCISCO—This year has been a “two for one deal,” with both semiconductors and chip manufacturing equipment cramming two typical years of growth into one year, resulting in overcapacity and ...