IEEE

Hardware Implementation of Systolic Array Architecture using 4:2 Compressor Approximate Multiplier for Image Processing Operations

Abstract: This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design ...
GitHub

Image Zoom - Streamlit Component

This repository presents a Python Streamlit component that wraps HTML, CSS, and JS code, enabling the creation of an interactive image zoom application. Try online demo! Note: Setting this parameter ...
IEEE

Infinity∞: Scaling Bitwise AutoRegressive Modeling for High-Resolution Image Synthesis

Abstract: We present Infinity, a Bitwise Visual AutoRegressive Modeling capable of generating high-resolution, photorealistic images following language instruction. Infinity refactors visual ...